As Complementary Metal Oxide Semiconductor (CMOS) technologies advance with smaller feature sizes and thinner gate oxides, power supply voltages have been scaled down to improve reliability and to conserve power. For MOS field effect transistors (MOSFETs), a thinner gate oxide corresponds to a faster device and to a lower voltage threshold. Even with operating voltages being reduced, some low voltage MOSFETs, which typically operate at 1.5 to 2.5 volts, must still interface with high voltage MOSFETs, which typically operate at 3.3 to 5 volts. There is also a need for high voltage MOSFETs to preform certain analog functions not easily performed at low voltage. Because MOSFETs can be designed to operate at different operating voltages for performing different functions, it is desirable for a semiconductor substrate to include different thicknesses of gate oxide layers to accommodate the different operating voltages.
Such a dual voltage semiconductor device is formed by growing two different gate oxide thicknesses. Thin gate oxides are grown for low voltage transistors, and thick gate oxides are grown for high voltage transistors. Furthermore, different gate oxide thicknesses require different doping levels under the gate oxide at the surface of the semiconductor substrate to obtain the correct transistor properties for the desired voltage threshold.
The extra processing steps needed to create a dual voltage semiconductor device may be performed by separately implanting high and low voltage active regions corresponding to the high and low voltage transistors to be formed therein. One approach is to mask off a portion of the semiconductor substrate to define the high voltage active regions. The high voltage active regions are defined by implanting impurities into the semiconductor substrate. This procedure typically requires three implantation steps. One for the well implant, one to suppress punch-through formation of the transistor, and a third to adjust a voltage threshold of the transistor. Once the high voltage active regions are defined, then the regions are masked off so that the additional implantation steps can be performed to define the low voltage active regions. Therefore, separately implanting high and low voltage active regions requires extra masking steps and repeated implantation steps to independently control definition of the high and low voltage transistors to be formed.
Instead of performing separate implantation steps for the high and low voltage active regions, another approach is to use a single mask to perform implantations that are common to both the high and low voltage active regions. This step avoids having to perform repeat implant steps. Common implantations include defining the wells and inhibiting or suppressing punch-through formation of the transistors. However, extra masks are required for performing the individual voltage threshold adjust implants for defining the particular thresholds of the high and low voltage transistors
The choice between using extra masks or performing repeated implantation steps for forming a desired dual voltage integrated circuit depends on the relative cost of photolithography processing versus the cost of performing implantation steps. Consequently, there is a continuing need to reduce processing costs in forming dual voltage integrated circuits, particularly through the reduction of masks and repeated implantation steps.